As the integration density of semiconductor devices has increased, the metal interconnect structure has become increasingly smaller in size. Accordingly, the structure of an interlayer dielectric (ILD) layer, (e.g., a pre-metal dielectric (PMD) layer), has been greatly changed.
FIG. 1 through FIG. 3 are cross-sectional views illustrating a conventional process of fabricating a semiconductor device. As shown in FIGS. 1-3, a semiconductor substrate 1 which has an active region defined by at least one device isolation layer 2 is prepared. Gate electrodes 5 comprising a gate insulating layer 3 and a polysilicon layer 4 are formed on the active region. Spacers 6 are then formed on both sidewalls of the gate electrodes 5. Impurities to form source/drain regions (not shown) are then implanted into the semiconductor substrate 1 by using the spacers 6 as a mask. Subsequently, an ILD layer, for example, a PMD layer 7, is deposited over the structure of FIG. 2. Contact holes 8 are formed through the PMD layer 7 and, then, filled with conductive material to form contact plugs 9. Metal interconnects 10 are formed over the PMD layer 7. The metal interconnects 10 are electrically connected to the gate electrodes 5 by the contact plugs 9 as shown in FIG. 3.
However, due to the high integration of the semiconductor device, the space D between adjacent gate electrodes 5 has increasingly been reduced. Therefore, filling the narrow gaps between the gate electrodes 5 becomes very difficult with conventional semiconductor fabrication technologies. More specifically, as the gaps between the gate electrodes 5 become narrow, the filling density of the PMD layer 7 between the gate electrodes 5 becomes low. As a result, defects such as voids are created in the PMD layer 7. Such defects may prevent the PMD layer 7 from completely insulating the gate electrodes 5 with respect to one another, thereby causing device deterioration due to insulation failure between the gate electrodes 5.
As an alternative, an aspect ratio (h to W) of the gate electrodes 5 may be decreased by reducing the thickness ‘h’ of the gate electrodes 5. This reduction in the aspect ration improves the filling density of the PMD layer 7 to some extent and, thus, suppresses or eliminates void formation in the PMD layer 7. In this approach, however, the resistance of the gate electrodes 5 is increased, which can cause another problem.
Accordingly, reliable solutions to overcome such problems have been sought by semiconductor industry. For example, Chen et al., U.S. Pat. No. 6,740,549, describe gate structures with sidewall spacers having improved profiles to suppress or eliminate defects between the gate structures during gap-filling. Chen et al. also describe a method of forming the gate structures over a semiconductor substrate. The method described in the Chen et al. Patent includes selectively depositing a liner over multi-layer gate stacks such that the liner is substantially thinner on a capping nitride layer than on a conductive layer, forming a nitride spacer over the liner, and forming a PMD layer over the resulting structure.